UVM

Table of Contents [wpbread] uvm_re_match Sometimes it is useful to use a regular expression within the testbench, such as filtering based on instance hierarchy. To do this, UVM has a function called uvm_pkg::uvm_re_match(), which is a DPI-C function that makes use of the POSIX function regexec() to perform a string match. import “DPI-C” function int uvm_re_match […]

[wpbread] UVM (Universal Verification Methodology) provides a framework for organizing the execution of a testbench into different phases, known as the UVM phases. The UVM phases help to structure the testbench creation and execution, making it easier to build and debug complex testbenches. UVM Phases also provide synchronizing mechanism for the environment. UVM phasing interface

uvm_config_db provides infrastructure to share configuration and other parameters between two or more testbench components or objects and it is the recommended way to access the resource database in UVM. uvm_config_db::set is used to put the information into the database uvm_config_db::get is used to retrieve the information from the database. This database can be populated and accessed using strings.

[wpbread] UVM(Universal Verification Methodology) is a standard methodology for verifying digital designs, primarily using the SystemVerilog language. It provides a library of base classes that can be used to build testbenches and test environments for verifying digital designs(DUT). The  UVM class hierarchy looks like- UVM is an open source code that provides: A library of